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preliminary copyright ? intel corporation, 1997 february 1997 order number: 272644-004 8XC196NU commercial chmos 16-bit microcontroller the 8XC196NU is a member of intels 16-bit mcs ? 96 microcontroller family. the device features 1 mbyte of linear address space, a demultiplexed bus, and a chip-select unit. the external bus can dynamically switch between multiplexed and demultiplexed operation. n 50 mhz operation ? n 1 mbyte of linear address space n optional 48 kbytes of rom n 1 kbyte of register ram n register-register architecture n footprint and functionally compatible upgrade for the 8xc196np n 32 i/o port pins n 16 prioritized interrupt sources n 4 external interrupt pins and nmi pin n 2 flexible 16-bit timer/counters with quadrature counting capability n 3 pulse-width modulator (pwm) outputs with high drive capability n full-duplex serial port with dedicated baud-rate generator n peripheral transaction server ? 40 mhz standard; 50 mhz is speed premium n chip-select unit 6 chip-select pins dynamic demultiplexed/multiplexed address/data bus for each chip select programmable wait states (0C3) for each chip select programmable bus width (8- or 16-bit) for each chip select programmable address range for each chip select n event processor array (epa) with 4 high-speed capture/compare channels n multiply and accumulate executes in 640 ns using the 32-bit hardware accumulator n 960 ns 32/16 unsigned division n 100-pin sqfp or 100-pin qfp package n complete system development support n high-speed chmos technology
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iii contents 8XC196NU commercial chmos 16-bit microcontroller 1.0 product overview ................................................................................................................ 1 2.0 nomenclature overview ...................................................................................................... 2 3.0 pinout .................................................................................................................................. 3 4.0 signals .............................................................................................................................. 12 5.0 address map ..................................................................................................................... 19 6.0 electrical characteristics ................................................................................................... 20 6.1 dc characteristics........................................................................................................ 21 6.2 ac characteristics........................................................................................................ 23 6.2.1 relationship of xtal1 to clkout .......................................................................23 6.2.2 explanation of ac symbols ...................................................................................24 6.2.3 ac characteristics multiplexed bus mode ........................................................25 6.2.4 ac characteristics demultiplexed bus mode ...................................................29 6.2.5 hold#, hlda# timings .......................................................................................34 6.2.6 ac characteristics serial port, synchronous mode 0 ......................................35 6.2.7 external clock drive ..............................................................................................36 7.0 thermal characteristics .................................................................................................... 38 8.0 8XC196NU errata ............................................................................................................ 38 9.0 datasheet revision history............................................................................................... 38 figures 1. 8XC196NU block diagram...................................................................................................1 2. the 8XC196NU family nomenclature .................................................................................2 3. 80c196nu 100-pin sqfp package.....................................................................................3 4. 80c196nu 100-pin qfp package .......................................................................................6 5. 83c196nu 100-pin qfp package .......................................................................................9 6. effect of clock mode on clkout......................................................................................23 7. system bus timings, multiplexed bus mode .....................................................................27 8. ready timing, multiplexed bus mode..............................................................................28 9. system bus timings, demultiplexed bus mode.................................................................31 10. ready timing, demultiplexed bus mode .........................................................................32 11. deferred bus mode timing diagram..................................................................................33 12. hold#, hlda# timing diagram .......................................................................................34 13. serial port waveform synchronous mode 0..................................................................35 14. external clock drive waveforms........................................................................................36 15. ac testing output waveforms during 5.0 volt testing .....................................................36 16. float waveforms during 5.0 volt testing...........................................................................37
8XC196NU commercial chmos 16-bit microcontroller iv tables 1. description of product nomenclature...................................................................................2 2. 80c196nu 100-pin sqfp pin assignment..........................................................................4 3. 80c196nu 100-pin sqfp pin assignment arranged by functional categories .................5 4. 80c196nu 100-pin qfp pin assignment ............................................................................7 5. 80c196nu 100-pin qfp pin assignment arranged by functional categories....................8 6. 83c196nu 100-pin qfp pin assignment ..........................................................................10 7. 83c196nu 100-pin qfp pin assignment arranged by functional categories..................11 8. signal descriptions ............................................................................................................12 9. 8XC196NU address map ...................................................................................................19 10. dc characteristics over specified operating conditions ..................................................21 11. ac timing symbol definitions............................................................................................24 12. ac characteristics the 8XC196NU will meet, multiplexed bus mode ...............................25 13. ac characteristics the external memory system must meet, multiplexed bus mode .......26 14. ac characteristics the 8XC196NU will meet, demultiplexed bus mode...........................29 15. ac characteristics the external memory system must meet, demultiplexed bus mode...30 16. hold#, hlda# timings ....................................................................................................34 17. serial port timing synchronous mode 0 .......................................................................35 18. external clock drive...........................................................................................................36 19. thermal characteristics .....................................................................................................38
preliminary 1 8XC196NU commercial chmos 16-bit microcontroller 1.0 product overview the 8XC196NU is a member of intels 16-bit mcs ? 96 microcontroller family. the device features 1 mbyte of linear address space, a demultiplexed bus, and a chip-select unit. the external bus can dynamically switch between multiplexed and demultiplexed operation. figure 1. 8XC196NU block diagram timer 1 timer 2 event processor array serial port baud rate gen port 2 port 1 port 1/ epa3:0, timer 1, timer 2 port 2/ hold control, sio, extint1:0 pulse width modulator microcode engine ralu cpu peripheral transaction server ad15:0 a15:0 a19:16/ eport3:0 chip select cs5:0# interrupt controller 16 16 8 1000 byte register file 24 bytes cpu sfrs memory controller with chip select queue port 3 port 4 port 3/ extint3:2 port 4/ pwm2:0 a2822-02 control signals 48 kbytes rom (optional)
2 preliminary 8XC196NU commercial chmos 16-bit microcontroller 2.0 nomenclature overview figure 2. the 8XC196NU family nomenclature table 1. description of product nomenclature parameter options description temperature and burn-in options no mark commercial operating temperature range (0c to 70c) with intel standard burn-in. packaging options sqfp sb sqfp programCmemory options 0 without rom 3rom process information c chmos product family 196nu device speed no mark 40 mhz 50 50 mhz program-memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options a2815-01 process information product family device speed
preliminary 3 8XC196NU commercial chmos 16-bit microcontroller 3.0 pinout figure 3. 80c196nu 100-pin sqfp package rd# bhe# / wrh# ale inst ready rpd once pllen2 v cc v ss a8 a9 a10 a11 a12 a13 a14 a15 nc v ss xtal1 xtal2 v ss v cc p2.7 / clkout ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 v cc ad8 v ss ad9 ad10 ad11 ad12 ad13 ad14 ad15 a16 / eport.0 a17 / eport.1 v cc v ss a18 / eport.2 a19 / eport.3 wr# / wrl# a2823-03 reset# nmi nc a0 a1 v cc v ss a2 a3 a4 a5 a6 a7 v cc v ss nc pllen1 p3.0 / cs0# p3.1 / cs1# p3.2 / cs2# p3.3 / cs3# v ss p3.4 / cs4# p3.5 / cs5# p3.6 / extint2 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 sb80c196nu view of component as mounted on pc board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p3.7 / extint3 p1.0 / epa0 v cc p1.1 / epa1 p1.2 / epa2 p1.3 / epa3 p1.4 / t1clk p1.5 / t1dir v cc p1.6 / t2clk v ss p1.7 / t2dir p4.0 / pwm0 p4.1 / pwm1 p4.2 / pwm2 p4.3 v cc v ss p2.0 / txd p2.1 / rxd p2.2 / extint0 p2.3 / breq# p2.4 / extint1 p2.5 / hold# p2.6 / hlda# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
4 preliminary 8XC196NU commercial chmos 16-bit microcontroller table 2. 80c196nu 100-pin sqfp pin assignment pin name pin name pin name pin name 1 reset# 26 extint3/p3.7 51 clkout/p2.7 76 wr#/wrl# 2 nmi 27 epa0/p1.0 52 v cc 77 eport.3/a19 3nc 28v cc 53 v ss 78 eport.2/a18 4 a0 29 epa1/p1.1 54 xtal2 79 v ss 5 a1 30 epa2/p1.2 55 xtal1 80 v cc 6v cc 31 epa3/p1.3 56 v ss 81 eport.1/a17 7v ss 32 t1clk/p1.4 57 nc 82 eport.0/a16 8 a2 33 t1dir/p1.5 58 a15 83 ad15 9a3 34v cc 59 a14 84 ad14 10 a4 35 t2clk/p1.6 60 a13 85 ad13 11 a5 36 v ss 61 a12 86 ad12 12 a6 37 t2dir/p1.7 62 a11 87 ad11 13 a7 38 pwm0/p4.0 63 a10 88 ad10 14 v cc 39 pwm1/p4.1 64 a9 89 ad9 15 v ss 40 pwm2/p4.2 65 a8 90 v ss 16 nc 41 p4.3 66 v ss 91 ad8 17 pllen1 42 v cc 67 v cc 92 v cc 18 cs0#/p3.0 43 v ss 68 pllen2 93 ad7 19 cs1#/p3.1 44 txd/p2.0 69 once 94 ad6 20 cs2#/p3.2 45 rxd/p2.1 70 rpd 95 ad5 21 cs3#/p3.3 46 extint0/p2.2 71 ready 96 ad4 22 v ss 47 breq#/p2.3 72 inst 97 ad3 23 cs4#/p3.4 48 extint1/p2.4 73 ale 98 ad2 24 cs5#/p3.5 49 hold#/p2.5 74 bhe#/wrh# 99 ad1 25 extint2/p3.6 50 hlda#/p2.6 75 rd# 100 ad0 note: to be compatible with future products, tie the nc (no connection) pins as follows: pin 57 = v ss , pin 16 = v cc , and pin 3 = nc.
preliminary 5 8XC196NU commercial chmos 16-bit microcontroller table 3. 80c196nu 100-pin sqfp pin assignment arranged by functional categories address & data address & data (continued) input/output power & ground name pin name pin name pin name pin a0 4 ad12 86 cs0#/p3.0 18 v cc 6 a1 5 ad13 85 cs1#/p3.1 19 v cc 14 a2 8 ad14 84 cs2#/p3.2 20 v cc 28 a3 9 ad15 83 cs3#/p3.3 21 v cc 34 a4 10 cs4#/p3.4 23 v cc 42 a5 11 bus control & status cs5#/p3.5 24 v cc 52 a6 12 name pin epa0/p1.0 27 v cc 67 a7 13 ale 73 epa1/p1.1 29 v cc 80 a8 65 bhe#/wrh# 74 epa2/p1.2 30 v cc 92 a9 64 breq# 47 epa3/p1.3 31 v ss 7 a10 63 hold# 49 eport.0 82 v ss 15 a11 62 hlda# 50 eport.1 81 v ss 22 a12 61 inst 72 eport.2 78 v ss 36 a13 60 rd# 75 eport.3 77 v ss 43 a14 59 ready 71 p2.2 46 v ss 53 a15 58 wr#/wrl# 76 p2.3 47 v ss 56 a16 82 p2.4 48 v ss 66 a17 81 processor control p2.5 49 v ss 79 a18 78 name pin p2.6 50 v ss 90 a19 77 clkout 51 p2.7 51 ad0 100 extint0 46 p3.6 25 no connection ad1 99 extint1 48 p3.7 26 name pin ad2 98 extint2 25 p4.3 41 nc 3 ad3 97 extint3 26 pwm0/p4.0 38 nc 16 ad4 96 nmi 2 pwm1/p4.1 39 nc 57 ad5 95 once 69 pwm2/p4.2 40 ad6 94 reset# 1 rxd/p2.1 45 ad7 93 rpd 70 t1clk/p1.4 32 ad8 91 xtal1 55 t1dir/p1.5 33 ad9 89 xtal2 54 t2clk/p1.6 35 ad10 88 pllen1 17 t2dir/p1.7 37 ad11 87 pllen2 68 txd/p2.0 44
6 preliminary 8XC196NU commercial chmos 16-bit microcontroller figure 4. 80c196nu 100-pin qfp package v ss a18 / eport.2 a19 / eport.3 wr# / wrl# rd# bhe# / wrh# ale inst ready rpd once pllen2 v cc v ss a8 a9 a10 a11 a12 a13 a14 a15 v ss xtal1 xtal2 v ss p2.7 / clkout v cc p2.6 / hlda# p2.5 / hold# ad1 ad2 ad3 ad4 ad5 ad6 ad7 v cc ad8 v ss ad9 ad10 ad11 ad12 ad13 ad14 ad15 a16 / eport.0 a17 / eport.1 v cc a2824-03 ad0 nc reset# nmi nc a0 a1 v cc v ss a2 a3 a4 a5 a6 a7 v cc v ss pllen1 p3.0 / cs0# p3.1 / cs1# p3.2 / cs2# p3.3 / cs3# v ss p3.4 / cs4# p3.5 / cs5# p3.6 / extint2 nc p3.7 / extint3 p1.0 / epa0 v cc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 s80c196nu view of component as mounted on pc board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p1.1 / epa1 p1.2 / epa2 p1.3 / epa3 p1.4 / t1clk p1.5 / t1dir v cc p1.6 / t2clk v ss p1.7 / t2dir p4.0 / pwm0 p4.1 / pwm1 p4.2 / pwm2 p4.3 v cc v ss p2.0 / txd p2.1 / rxd p2.2 / extint0 p2.3 / breq# p2.4 / extint1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
preliminary 7 8XC196NU commercial chmos 16-bit microcontroller table 4. 80c196nu 100-pin qfp pin assignment pin name pin name pin name pin name 1 ad0 26 extint2/p3.6 51 hold#/p2.5 76 rd# 2 nc 27nc 52hlda#/p2.6 77wr#/wrl# 3 reset# 28extint3/p3.7 53v cc 78 eport.3/a19 4 nmi 29 epa0/p1.0 54 clkout/p2.7 79 eport.2/a18 5nc 30v cc 55 v ss 80 v ss 6 a0 31 epa1/p1.1 56 xtal2 81 v cc 7 a1 32 epa2/p1.2 57 xtal1 82 eport.1/a17 8v cc 33 epa3/p1.3 58 v ss 83 eport.0/a16 9v ss 34 t1clk/p1.4 59 a15 84 ad15 10 a2 35 t1dir/p1.5 60 a14 85 ad14 11 a3 36 v cc 61 a13 86 ad13 12 a4 37 t2clk/p1.6 62 a12 87 ad12 13 a5 38 v ss 63 a11 88 ad11 14 a6 39 t2dir/p1.7 64 a10 89 ad10 15 a7 40 pwm0/p4.0 65 a9 90 ad9 16 v cc 41 pwm1/p4.1 66 a8 91 v ss 17 v ss 42 pwm2/p4.2 67 v ss 92 ad8 18 pllen1 43 p4.3 68 v cc 93 v cc 19 cs0#/p3.0 44 v cc 69 pllen2 94 ad7 20 cs1#/p3.1 45 v ss 70 once 95 ad6 21 cs2#/p3.2 46 txd/p2.0 71 rpd 96 ad5 22 cs3#/p3.3 47 rxd/p2.1 72 ready 97 ad4 23 v ss 48 extint0/p2.2 73 inst 98 ad3 24 cs4#/p3.4 49 breq#/p2.3 74 ale 99 ad2 25 cs5#/p3.5 50 extint1/p2.4 75 bhe#/wrh# 100 ad1 note: to be compatible with future proliferations, tie the nc (no connect) pin as follows: pin 2 = v ss pin 5 = ea# on products with internal memory (v cc = internal memory, v ss = external memory) pin 27 = v cc
8 preliminary 8XC196NU commercial chmos 16-bit microcontroller table 5. 80c196nu 100-pin qfp pin assignment arranged by functional categories address & data address & data (continued) input/output power & ground name pin name pin name pin name pin a0 6 ad12 87 cs0#/p3.0 19 v cc 8 a1 7 ad13 86 cs1#/p3.1 20 v cc 16 a2 10 ad14 85 cs2#/p3.2 21 v cc 30 a3 11 ad15 84 cs3#/p3.3 22 v cc 36 a4 12 cs4#/p3.4 24 v cc 44 a5 13 bus control & status cs5#/p3.5 25 v cc 53 a6 14 name pin epa0/p1.0 29 v cc 68 a7 15 ale 74 epa1/p1.1 31 v cc 81 a8 66 bhe#/wrh# 75 epa2/p1.2 32 v cc 93 a9 65 breq# 49 epa3/p1.3 33 v ss 9 a10 64 hold# 51 eport.0 83 v ss 17 a11 63 hlda# 52 eport.1 82 v ss 23 a12 62 inst 73 eport.2 79 v ss 38 a13 61 rd# 76 eport.3 78 v ss 45 a14 60 ready 72 p2.2 48 v ss 55 a15 59 wr#/wrl# 77 p2.3 49 v ss 58 a16 83 p2.4 50 v ss 67 a17 82 processor control p2.5 51 v ss 80 a18 79 name pin p2.6 52 v ss 91 a19 78 clkout 54 p2.7 54 ad0 1 extint0 48 p3.6 26 no connection ad1 100 extint1 50 p3.7 28 name pin ad2 99 extint2 26 p4.3 43 nc 2 ad3 98 extint3 28 pwm0/p4.0 40 nc 5 ad4 97 nmi 4 pwm1/p4.1 41 nc 27 ad5 96 once 70 pwm2/p4.2 42 ad6 95 reset# 3 rxd/p2.1 47 ad7 94 rpd 71 t1clk/p1.4 34 ad8 92 xtal1 57 t1dir/p1.5 35 ad9 90 xtal2 56 t2clk/p1.6 37 ad10 89 pllen1 18 t2dir/p1.7 39 ad11 88 pllen2 69 txd/p2.0 46
preliminary 9 8XC196NU commercial chmos 16-bit microcontroller figure 5. 83c196nu 100-pin qfp package v ss a18 / eport.2 a19 / eport.3 wr# / wrl# rd# bhe# / wrh# ale inst ready rpd once pllen2 v cc v ss a8 a9 a10 a11 a12 a13 a14 a15 v ss xtal1 xtal2 v ss p2.7 / clkout v cc p2.6 / hlda# p2.5 / hold# ad1 ad2 ad3 ad4 ad5 ad6 ad7 v cc ad8 v ss ad9 ad10 ad11 ad12 ad13 ad14 ad15 a16 / eport.0 a17 / eport.1 v cc a3217-02 ad0 nc reset# nmi ea# a0 a1 v cc v ss a2 a3 a4 a5 a6 a7 v cc v ss pllen1 p3.0 / cs0# p3.1 / cs1# p3.2 / cs2# p3.3 / cs3# v ss p3.4 / cs4# p3.5 / cs5# p3.6 / extint2 nc p3.7 / extint3 p1.0 / epa0 v cc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 s83c196nu view of component as mounted on pc board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p1.1 / epa1 p1.2 / epa2 p1.3 / epa3 p1.4 / t1clk p1.5 / t1dir v cc p1.6 / t2clk v ss p1.7 / t2dir p4.0 / pwm0 p4.1 / pwm1 p4.2 / pwm2 p4.3 v cc v ss p2.0 / txd p2.1 / rxd p2.2 / extint0 p2.3 / breq# p2.4 / extint1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
10 preliminary 8XC196NU commercial chmos 16-bit microcontroller table 6. 83c196nu 100-pin qfp pin assignment pin name pin name pin name pin name 1 ad0 26 extint2/p3.6 51 hold#/p2.5 76 rd# 2 nc 27nc 52hlda#/p2.6 77wr#/wrl# 3 reset# 28 extint3/p3.7 53 v cc 78 eport.3/a19 4 nmi 29 epa0/p1.0 54 clkout/p2.7 79 eport.2/a18 5 ea# 30 v cc 55 v ss 80 v ss 6 a0 31 epa1/p1.1 56 xtal2 81 v cc 7 a1 32 epa2/p1.2 57 xtal1 82 eport.1/a17 8v cc 33 epa3/p1.3 58 v ss 83 eport.0/a16 9v ss 34 t1clk/p1.4 59 a15 84 ad15 10 a2 35 t1dir/p1.5 60 a14 85 ad14 11 a3 36 v cc 61 a13 86 ad13 12 a4 37 t2clk/p1.6 62 a12 87 ad12 13 a5 38 v ss 63 a11 88 ad11 14 a6 39 t2dir/p1.7 64 a10 89 ad10 15 a7 40 pwm0/p4.0 65 a9 90 ad9 16 v cc 41 pwm1/p4.1 66 a8 91 v ss 17 v ss 42 pwm2/p4.2 67 v ss 92 ad8 18 pllen1 43 p4.3 68 v cc 93 v cc 19 cs0#/p3.0 44 v cc 69 pllen2 94 ad7 20 cs1#/p3.1 45 v ss 70 once 95 ad6 21 cs2#/p3.2 46 txd/p2.0 71 rpd 96 ad5 22 cs3#/p3.3 47 rxd/p2.1 72 ready 97 ad4 23 v ss 48 extint0/p2.2 73 inst 98 ad3 24 cs4#/p3.4 49 breq#/p2.3 74 ale 99 ad2 25 cs5#/p3.5 50 extint1/p2.4 75 bhe#/wrh# 100 ad1 note: to be compatible with future proliferations, tie the nc (no connect) pins as follows: pin 2 = v ss pin 27 = v cc .
preliminary 11 8XC196NU commercial chmos 16-bit microcontroller table 7. 83c196nu 100-pin qfp pin assignment arranged by functional categories address & data address & data (continued) input/output power & ground name pin name pin name pin name pin a0 6 ad12 87 cs0#/p3.0 19 v cc 8 a1 7 ad13 86 cs1#/p3.1 20 v cc 16 a2 10 ad14 85 cs2#/p3.2 21 v cc 30 a3 11 ad15 84 cs3#/p3.3 22 v cc 36 a4 12 bus control & status cs4#/p3.4 24 v cc 44 a5 13 name pin cs5#/p3.5 25 v cc 53 a6 14 ale 74 epa0/p1.0 29 v cc 68 a7 15 bhe#/wrh# 75 epa1/p1.1 31 v cc 81 a8 66 breq# 49 epa2/p1.2 32 v cc 93 a9 65 hold# 51 epa3/p1.3 33 v ss 9 a10 64 hlda# 52 eport.0 83 v ss 17 a11 63 inst 73 eport.1 82 v ss 23 a12 62 rd# 76 eport.2 79 v ss 38 a13 61 ready 72 eport.3 78 v ss 45 a14 60 wr#/wrl# 77 p2.2 48 v ss 55 a15 59 p2.3 49 v ss 58 a16 83 processor control p2.4 50 v ss 67 a17 82 name pin p2.5 51 v ss 80 a18 79 clkout 54 p2.6 52 v ss 91 a19 78 extint0 48 p2.7 54 ad0 1 extint1 50 p3.6 26 no connection ad1 100 extint2 26 p3.7 28 name pin ad2 99 extint3 28 p4.3 43 nc 2 ad3 98 nmi 4 pwm0/p4.0 40 nc 27 ad4 97 once 70 pwm1/p4.1 41 ad5 96 reset# 3 pwm2/p4.2 42 ad6 95 rpd 71 rxd/p2.1 47 ad7 94 xtal1 57 t1clk/p1.4 34 ad8 92 xtal2 56 t1dir/p1.5 35 ad9 90 pllen1 18 t2clk/p1.6 37 ad10 89 pllen2 69 t2dir/p1.7 39 ad11 88 ea# 5 txd/p2.0 46
12 preliminary 8XC196NU commercial chmos 16-bit microcontroller 4.0 signals table 8. signal descriptions name type description a15:0 i/o system address bus these address lines provide address bits 0C15 during the entire external mem- ory cycle during both multiplexed and demultiplexed bus m odes. a19:16 i/o address lines 16C19 these address lines provide address bits 16C19 during the entire external memory cycle, supporting extended addressing of the 1 mbyte address space. note: internally, there are 24 address bits; however, only 20 external address pins (a19:0) are implemented. the internal address space is 16 mbytes (000000Cffffffh) and the external address space is 1 mbyte (00000Cfffffh). the device resets to ff2080h in internal memory or f2080h in external memory. a19:16 are multiplexed with eport.3:0. ad15:0 i/o address/data lines the functions of these pins depend on the bus size and mode. when a bus access is not occurring, these pins revert to their i/o port function. 16-bit multiplexed bus mode : ad15:0 drive address bits 0C15 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 8-bit multiplexed bus mode : ad15:8 drive address bits 8C15 during the entire bus cycle. ad7:0 drive address bits 0C7 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 16-bit demultiplexed mode : ad15:0 drive or receive data during the entire bus cycle. 8-bit demultiplexed mode : ad7:0 drive or receive data during the entire bus cycle. ad15:8 drive the data that is currently on the high byte of the internal bus. ale o address latch enable this active-high output signal is asserted only during external memory cycles. ale signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (a19:16 and ad15:0 for a multiplexed bus; a19:0 for a demultiplexed bus). ale differs from adv# in that it does not remain active during the entire bus cycle. an external latch can use this signal to demultiplex the address bits 0C15 from the address/data bus in multiplexed mode.
preliminary 13 8XC196NU commercial chmos 16-bit microcontroller bhe# o byte high enable ? during 16-bit bus cycles, this active-low output signal is asserted for word reads and writes and high-byte reads and writes to external memory. bhe# indicates that valid data is being transferred over the upper half of the system data bus. use bhe#, in conjunction with a0, to determine which memory byte is being transferred over the system bus: bhe# a0 byte(s) accessed 0 0 both bytes 0 1 high byte only 1 0 low byte only bhe# is multiplexed with wrh#. ? the chip configuration register 0 (ccr0) determines whether this pin func- tions as bhe# or wrh#. ccr0.2 = 1 selects bhe#; ccr0.2 = 0 selects wrh#. breq# o bus request this active-low output signal is asserted during a hold cycle when the bus con- troller has a pending external memory cycle. when the bus-hold protocol is enabled (wsr.7 is set), the p2.3/breq# pin can function only as breq#, regardless of the configuration selected through the port configuration registers (p2_mode, p2_dir, and p2_reg). an attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (wsr.7 is cleared). breq# is multiplexed with p2.3. clkout o clock output output of the internal clock generator. the clkout frequency is ? the internal operating frequency (f). clkout has a 50% duty cycle. clkout is multiplexed with p2.7. cs5#:0 o chip-select lines 0C5 the active-low output cs x # is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x . if the external memory address is outside the range assigned to the six chip selects, no chip-select output is asserted and the bus configuration defaults to the cs5# values. immediately following reset, cs0# is automatically assigned to the range ff2000Cff20ffh (f2000Cf20ffh if external). cs5:0# is multiplexed with p3.5:0. ea# i external access this active-low input signal determines whether memory accesses to special purpose and program memory partitions (ff2000Cffdfffh) are directed to internal or external memory. these memory accesses are directed to internal memory if ea# is deasserted and to external memory if ea# is asserted. for an access to any other memory location, the value of ea# is irrelevant. ea# is not latched and can be switched dynamically during normal operating mode. be sure to thoroughly consider the issues, such as different access times for internal and external memory, before using this dynamic switching capability. always connect ea# to v ss when using a microcontroller that has no internal nonvolatile memory. table 8. signal descriptions (continued) name type description
14 preliminary 8XC196NU commercial chmos 16-bit microcontroller epa3:0 i/o event processor array (epa) input/output pins these are the high-speed input/output pins for the epa capture/compare chan- nels. for high-speed pwm applications, the outputs of two epa channels (either epa0 and epa1 or epa2 and epa3) can be remapped to produce a pwm wave- form on a shared output pin. epa3:0 are multiplexed with p1.3:0. eport.3:0 i/o extended addressing port this is a standard, 4-bit, bidirectional i/o port. eport.3:0 are multiplexed with a19:16. extint3:0 i external interrupts in normal operating mode, a rising edge on extint x sets the extint x inter- rupt pending bit. extint x is sampled during phase 2 (clkout high). the min- imum high time is one state time. in standby and powerdown modes, asserting the extint x signal for at least 50 ns causes the device to resume normal operation. the interrupt need not be enabled, but the pin must be configured as a special-function input. if the extint x interrupt is enabled, the cpu executes the interrupt service routine. otherwise, the cpu executes the instruction that immediately follows the com- mand that invoked the power-saving mode. in idle mode, asserting any enabled interrupt causes the device to resume nor- mal operation. extint0 is multiplexed with p2.2, extint1 is multiplexed with p2.4, extint2 is multiplexed with p3.6, and extint3 is multiplexed with p3.7. hlda# o bus hold acknowledge this active-low output indicates that the cpu has released the bus as the result of an external device asserting hold#. when the bus-hold protocol is enabled (wsr.7 is set), the p2.6/hlda# pin can function only as hlda#, regardless of the configuration selected through the port configuration registers (p2_mode, p2_dir, and p2_reg). an attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (wsr.7 is cleared). hlda# is multiplexed with p2.6. hold# i bus hold request an external device uses this active-low input signal to request control of the bus. when the bus-hold protocol is enabled (wsr.7 is set), the p2.5/hold# pin can function only as hold#, regardless of the configuration selected through the port configuration registers (p2_mode, p2_dir, and p2_reg). an attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (wsr.7 is cleared). hold# is multiplexed with p2.5. inst o instruction fetch this active-high output signal is valid only during external memory bus cycles. when high, inst indicates that an instruction is being fetched from external memory. the signal remains high during the entire bus cycle of an external instruction fetch. inst is low for data accesses, including interrupt vector fetches and chip configuration byte reads. inst is low during internal memory fetches. table 8. signal descriptions (continued) name type description
preliminary 15 8XC196NU commercial chmos 16-bit microcontroller nmi i nonmaskable interrupt in normal operating mode, a rising edge on nmi generates a nonmaskable interrupt. nmi has the highest priority of all prioritized interrupts. assert nmi for greater than one state time to guarantee that it is recognized. once i on-circuit emulation holding once high during the rising edge of reset# places the device into on-circuit emulation (once) mode. this mode puts all pins into a high-imped- ance state, thereby isolating the device from other components in the system. the value of once is latched when the reset# pin goes inactive. while the device is in once mode, you can debug the system using a clip-on emulator. to exit once mode, reset the device by pulling the reset# signal low. to pre- vent accidental entry into once mode, connect the once pin to v ss . p1.7:0 i/o port 1 this is a standard bidirectional port that is multiplexed with individually select- able special-function signals. port 1 is multiplexed as follows: p1.0/epa0, p1.1/epa1, p1.2/epa2, p1.3/epa3, p1.4/t1clk, p1.5/t1dir, p1.6/t2clk, and p1.7/t2dir. p2.7:0 i/o port 2 this is a standard bidirectional port that is multiplexed with individually select- able special-function signals. port 2 is multiplexed as follows: p2.0/txd, p2.1/rxd, p2.2/extint0, p2.3/ breq#, p2.4/extint1, p2.5/hold#, p2.6/hlda#, and p2.7/clkout. p3.7:0 i/o port 3 this is an 8-bit, bidirectional, standard i/o port. port 3 is multiplexed as follows: p3.0/cs0#, p3.1/cs1#, p3.2/cs2#, p3.3/ cs3#, p3.4/cs4#, p3.5/cs5#, p3.6/extint2, and p3.7/extint3. p4.3:0 i/o port 4 this is a 4-bit, bidirectional, standard i/o port with high-current drive capability. port 4 is multiplexed as follows: p4.0/pwm0, p4.1/pwm1, and p4.2/pwm2. p4.3 is not multiplexed. pllen2:1 i phase-locked loop 1 and 2 enable these input pins are used to enable the on-chip clock multiplier feature and select either the doubled or quadrupled clock speed as follows: pllen2 pllen1 mode 0 0 standard mode; clock multiplier circuitry disabled. internal clock equals the xtal1 input frequency. 10reserved ? 0 1 doubled mode; clock multiplier circuitry enabled. internal clock is twice the xtal1 input frequency. 1 1 quadrupled mode; clock multiplier circuitry enabled. internal clock is four times the xtal1 input frequency. ? this reserved combination causes the device to enter an unsupported test mode. table 8. signal descriptions (continued) name type description
16 preliminary 8XC196NU commercial chmos 16-bit microcontroller pwm2:0 o pulse width modulator outputs these are pwm output pins with high-current drive capability. the duty cycle and frequency-pulse-widths are programmable. pwm2:0 are multiplexed with p4.2:0. rd# o read read-signal output to external memory. rd# is asserted only during external memory reads. ready i ready input this active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally. when ready is high, cpu operation continues in a normal manner with wait states inserted as programmed in the chip configuration registers or the chip- select x bus control register. ready is ignored for all internal memory accesses. reset# i/o reset a level-sensitive reset input to and open-drain system reset output from the microcontroller. either a falling edge on reset# or an internal reset turns on a pull-down transistor connected to the reset# pin for 16 state times. in the powerdown, standby, and idle modes, asserting reset# causes the chip to reset and return to normal operating mode. if the phase-locked loop (pll) clock circuitry is enabled, you must hold reset# low for at least 2 ms to allow the pll to stabilize before the internal cpu and peripheral clocks are enabled. after a device reset, the first instruction fetch is from ff2080h (or f2080h in external memory). the program and special-purpose memory locations (ff2000Cff2fffh) reside in external memory. rpd i return from powerdown timing pin for the return-from-powerdown circuit. if your application uses powerdown mode, connect a capacitor between rpd and v ss if either of the following conditions is true: ? the internal oscillator is the clock source ? the phase-locked loop (pll) circuitry is enabled (see pllen2:1 signal description) the capacitor causes a delay that enables the oscillator and pll circuitry to stabilize before the internal cpu and peripheral clocks are enabled. the capacitor is not required if your application uses powerdown mode and if both of the following conditions are true: ? an external clock input is the clock source ? the phase-locked loop circuitry is disabled if your application does not use powerdown mode, leave this pin unconnected. rxd i/o receive serial data in modes 1, 2, and 3, rxd receives serial port input data. in mode 0, it func- tions as either an input or an open-drain output for data. rxd is multiplexed with p2.1. table 8. signal descriptions (continued) name type description
preliminary 17 8XC196NU commercial chmos 16-bit microcontroller t1clk i timer 1 external clock external clock for timer 1. timer 1 increments (or decrements) on both rising and falling edges of t1clk. also used in conjunction with t1dir for quadrature counting mode. and external clock for the serial i/o baud-rate generator input (program selectable). t1clk is multiplexed with p1.4. t2clk i timer 2 external clock external clock for timer 2. timer 2 increments (or decrements) on both rising and falling edges of t2clk. also used in conjunction with t2dir for quadrature counting mode. t2clk is multiplexed with p1.6. t1dir i timer 1 external direction external direction (up/down) for timer 1. timer 1 increments when t1dir is high and decrements when it is low. also used in conjunction with t1clk for quadra- ture counting mode. t1dir is multiplexed with p1.5. t2dir i timer 2 external direction external direction (up/down) for timer 2. timer 2 increments when t2dir is high and decrements when it is low. also used in conjunction with t2clk for quadra- ture counting mode. t2dir is multiplexed with p1.7. txd o transmit serial data in serial i/o modes 1, 2, and 3, txd transmits serial port output data. in mode 0, it is the serial clock output. txd is multiplexed with p2.0. v cc pwr digital supply voltage connect each v cc pin to the digital supply voltage. v ss gnd digital circuit ground connect each v ss pin to ground through the lowest possible impedance path. wr# o write ? this active-low output indicates that an external write is occurring. this signal is asserted only during external memory writes. wr# is multiplexed with wrl#. ? the chip configuration register 0 (ccr0) determines whether this pin func- tions as wr# or wrl#. ccr0.2 = 1 selects wr#; ccr0.2 = 0 selects wrl#. wrh# o write high ? during 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. during 8-bit bus cycles, wrh# is asserted for all write operations. wrh# is multiplexed with bhe#. ? the chip configuration register 0 (ccr0) determines whether this pin func- tions as bhe# or wrh#. ccr0.2 = 1 selects bhe#; ccr0.2 = 0 selects wrh#. table 8. signal descriptions (continued) name type description
18 preliminary 8XC196NU commercial chmos 16-bit microcontroller wrl# o write low ? during 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes. during 8-bit bus cycles, wrl# is asserted for all write operations. wrl# is multiplexed with wr#. ? the chip configuration register 0 (ccr0) determines whether this pin func- tions as wr# or wrl#. ccr0.2 = 1 selects wr#; ccr0.2 = 0 selects wrl#. xtal1 i input crystal/resonator or external clock input input to the on-chip oscillator, phase-locked loop circuitry, and the internal clock generators. the internal clock generators provide the peripheral clocks, cpu clock, and clkout signal. when using an external clock source instead of the on-chip oscillator, connect the clock input to xtal1. the external clock signal must meet the v ih specification for xtal1 (see datasheet). xtal2 o inverted output for the crystal/resonator output of the on-chip oscillator inverter. leave xtal2 floating when the design uses a external clock source instead of the on-chip oscillator. table 8. signal descriptions (continued) name type description
preliminary 19 8XC196NU commercial chmos 16-bit microcontroller 5.0 address map table 9. 8XC196NU address map hex address description addressing modes ff ffffh ff e000h external device (memory or i/o) connected to address/data bus indirect, indexed, extended ff dfffh ff 2080h program memory (note 1) indirect, indexed, extended ff 207fh ff 2000h special-purpose memory (note 1) indirect, indexed, extended ff 1fffh ff 0100h external device (memory or i/o) connected to address/data bus indirect, indexed, extended ff 00ffh ff 0000h reserved for ice (note 2) fe ffffh 0f 0000h overlaid memory (reserved for future devices) (note 2) indirect, indexed, extended 0e ffffh 01 0000h external device (memory or i/o) connected to address/data bus indirect, indexed, extended 00 ffffh 00 e000h external device (memory or i/o) connected to address/data bus indirect, indexed, extended 00 dfffh 00 2000h external device (memory or i/o) connected to address/data bus or remapped internal rom (determined by ea# pin) (note 3) indirect, indexed, extended 00 1fffh 00 1f00h internal peripheral special-function registers (sfrs) (note 4) indirect, indexed, extended, windowed direct 00 1effh 00 0400h external device (memory or i/o) connected to address/data bus indirect, indexed, extended 00 03ffh 00 0100h upper register file (general-purpose register ram) indirect, indexed, windowed direct 00 00ffh 00 001ah lower register file (general-purpose register ram) direct, indirect, indexed, windowed direct 00 0019h 00 0018h lower register file (stack pointer) direct, indirect, indexed, windowed direct 00 0017h 00 0000h lower register file (cpu sfrs) (note 4) direct, indirect, indexed, windowed direct notes: 1. for the 80c196nu, the program and special-purpose memory locations (ff2000Cffdfffh) reside in external memory. for the 83c196nu, these locations can reside either in external memory or in internal rom. 2. locations x f0000C x f00ffh are reserved, write 0ffh to these locations. 3. for the 80c196nu, this address range (ff2080Cffdfffh) is always external memory. for the 83c196nu, this address range is mapped into internal rom if the remap bit (ccb1.2) is set and ea# is at logic 1. otherwise, they are mapped to external memory. 4. unless otherwise noted, write 0 to reserved sfr bits.
20 preliminary 8XC196NU commercial chmos 16-bit microcontroller 6.0 electrical characteristics absolute maximum ratings* storage temperature ................................... C60c to +150c supply voltage with respect to v ss ............... C0.5 v to +7.0 v power dissipation ........................................................... 1.5 w operating conditions* t a (ambient temperature under bias) ................ 0c to +70c v cc (digital supply voltage) ............................. 4.5 v to 5.5 v f xtal 1 (input frequency for v cc = 4.5 v C 5.5 v) (note 1, 2, 3)........................................ 16 mhz to 50 mhz notes: 1. this device is static and should operate below 1 hz, but has been tested only down to 16 mhz. 2. the maximum crystal that can be used is 25 mhz. 3. the minimum xtal1 frequency when using the pll is 8 mhz. notice : this document contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning : stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability.
preliminary 21 8XC196NU commercial chmos 16-bit microcontroller 6.1 dc characteristics table 10. dc characteristics over specified operating conditions symbol parameter min typical (note 1) max units test conditions i cc v cc supply current 90 120 ma xtal1 = 50 mhz v cc = 5.5 v device in reset i idle idle mode current 45 60 ma xtal1 = 50 mhz v cc = 5.5 v i pd powerdown mode current 20 50 a v cc = 5.5 v (note 2) i stdby standby mode 8 15 ma v cc = 5.5 v i li input leakage current (standard inputs) 10 a v ss < v in < v cc v il input low voltage (all pins) C0.5 0.8 v v ih input high voltage 0.2 v cc + 1 v cc + 0.5 v v il 1 input low voltage xtal1 C0.5 0.3 v cc v v ih 1 input high voltage xtal1 0.7 v cc v cc + 0.5 v v ih 2 input high voltage (reset pin) (note 3) 0.2 v cc + 1.4 v cc + 0.5 v v ol output low voltage (output configured as complemen- tary) (note 4, 5) 0.3 0.45 1.5 v v v i ol = 200 a i ol = 3.2 ma i ol = 7.0 ma v oh output high voltage (output configured as complemen- tary) (note 5) v cc C 0.3 v cc C 0.7 v cc C 1.5 v v v i oh = C200 a i oh = C3.2 ma i oh = C7.0 ma notes: 1. typical values are based on a limited number of samples and are not guaranteed. the values listed are at room temperature with v cc = 5.0 v. 2. for temperatures below 100 c , typical is 10 a. 3. b-step only. 4. for all pins except p4.3:0, which have higher drive capability (see v ol 1 ). 5. during normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: group i ol (ma) i oh (ma) individual i ol (ma) i oh (ma) p1.7:3, p4 40 40 p1, p2, p3 10 10 p2 40 40 p4 18 10 p1.2:0, p3 40 40 6. for all pins that were weakly pulled high during reset. this excludes ale, inst, and nmi, which were weakly pulled low (see v ol 2 ) and once, which was pulled medium low (see v ol 3 ). 7. pin capacitance is not tested. this value is based on design simulations.
22 preliminary 8XC196NU commercial chmos 16-bit microcontroller v ol 1 output low voltage on p4. x (output configured as com- plementary) (note 5) 0.45 0.6 v v i ol = 10 ma i ol = 15 ma v ol 2 output low voltage in reset on ale, inst, and nmi 0.45 v i ol = 3 a v oh 1 output high voltage in reset (note 6) v cc C 0.7 v i oh = C3 a v ol 3 output low voltage in reset for once pin 0.45 v i ol = 30 a v ol 4 output low voltage on xtal2 0.3 0.45 1.5 v v v i ol = 100 a i ol = 700 a i ol = 3 ma v oh 2 output high voltage on xtal2 v cc C 0.3 v cc C 0.7 v cc C 1.5 v v v i oh = C100 a i oh = C700 a i oh = C3 ma v th + C v th C hysteresis voltage width on reset# pin 0.3 v c s pin capacitance (any pin to v ss ) (note 7) 10 pf r rst reset pull-up resistor 9 95 k w v cc = 5.5 v, v in = 4.0 v table 10. dc characteristics over specified operating conditions (continued) symbol parameter min typical (note 1) max units test conditions notes: 1. typical values are based on a limited number of samples and are not guaranteed. the values listed are at room temperature with v cc = 5.0 v. 2. for temperatures below 100 c , typical is 10 a. 3. b-step only. 4. for all pins except p4.3:0, which have higher drive capability (see v ol 1 ). 5. during normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: group i ol (ma) i oh (ma) individual i ol (ma) i oh (ma) p1.7:3, p4 40 40 p1, p2, p3 10 10 p2 40 40 p4 18 10 p1.2:0, p3 40 40 6. for all pins that were weakly pulled high during reset. this excludes ale, inst, and nmi, which were weakly pulled low (see v ol 2 ) and once, which was pulled medium low (see v ol 3 ). 7. pin capacitance is not tested. this value is based on design simulations.
preliminary 23 8XC196NU commercial chmos 16-bit microcontroller 6.2 ac characteristics 6.2.1 relationship of xtal1 to clkout figure 6. effect of clock mode on clkout clkout clkout t = 80ns t = 40ns t = 20ns clkout t xhch xtal1 (12.5 mhz) f pllen2:1=01 f pllen2:1=11 f pllen2:1=00 a3160-02
24 preliminary 8XC196NU commercial chmos 16-bit microcontroller 6.2.2 explanation of ac symbols each ac timing symbol is two pairs of letters prefixed by t for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. table 11. ac timing symbol definitions character signal(s) a ad15:0, a19:0 bbhe# cclkout d ad15:0, ad7:0 hhold# ha hlda# lale q ad15:0, ad7:0 r rd# scs x # wwr#, wrl# x xtal1, yready character condition h high llow v valid x no longer valid z floating (low impedance)
preliminary 25 8XC196NU commercial chmos 16-bit microcontroller 6.2.3 ac characteristics multiplexed bus mode test conditions: capacitive load on all pins = 50 pf, rise and fall times = 3 ns. table 12. ac characteristics the 8XC196NU will meet, multiplexed bus mode symbol parameter min max units f xtal 1 frequency on xtal1, pll in 1x mode 16 50 (1) mhz frequency on xtal1, pll in 2x mode 8 (2) 25 mhz frequency on xtal1, pll in 4x mode 8 (2) 12.5 mhz f operating frequency, f = f xtal 1 ; pll in 1x mode 16 50 mhz operating frequency, f = 2f xtal 1 ; pll in 2x mode operating frequency, f = 4f xtal 1 ; pll in 4x mode t period, t = 1/f 20 62.5 ns t xhch xtal1 rising edge to clkout high or low 3 50 ns t clcl clkout cycle time 2t ns t chcl clkout high period t C 10 t + 15 ns t avwl address valid to wr# falling edge 2t C 25 ns t cllh clkout falling edge to ale rising edge C 10 10 ns t llch ale falling edge to clkout rising edge C 15 15 ns t lhlh ale cycle time 4t ns (3) t lhll ale high period t C 10 t + 10 ns t avll address valid to ale falling edge t C 14 ns t llax address hold after ale falling edge t C 10 ns t llrl ale falling edge to rd# falling edge t C 15 ns t rlcl rd# low to clkout falling edge C 10 20 ns t rlrh rd# low period t C 10 ns (3) t rhlh rd# rising edge to ale rising edge t C 5 t + 15 ns (4) t rlaz rd# low to address float 5 ns t llwl ale falling edge to wr# falling edge t C 11 ns t qvwh data stable to wr# rising edge t C 14 ns ( 3 ) t chwh clkout high to wr# rising edge C 15 5 ns notes: 1. 25 mhz is the maximum input frequency when using an external crystal oscillator; however, 50 mhz can be applied with an external clock source. 2. when the phase-locked loop (pll) circuitry is enabled, the minimum input frequency on xtal1 is 8 mhz. the pll cannot be run at frequencies lower than 16 mhz. 3. if wait states are used, add 2t n , where n = number of wait states. 4. assuming back-to-back bus cycles. 5. 8-bit bus only.
26 preliminary 8XC196NU commercial chmos 16-bit microcontroller t wlwh wr# low period t C 10 ns (3) t whqx data hold after wr# rising edge t C 7 ns t whlh wr# rising edge to ale rising edge t C 14 t + 20 ns t whbx bhe#, inst hold after wr# rising edge a-step b-step t C 4 0 ns t whax ad15:8 hold after wr# rising edge t C 4 ns (5) t rhbx bhe#, inst hold after rd# rising edge a-step b-step t 0 ns t rhax ad15:8 hold after rd# rising edge t ns (5) t w hsh a19:16, cs# hold after wr# rising edge 0 ns t rhsh a19:16, cs# hold after rd# rising edge 0 ns table 13. ac characteristics the external memory system must meet, multiplexed bus mode symbol parameter min max units t avdv ad15:0 valid to input data valid 3t C 32 ns (1) t rldv rd# active to input data valid t C 22 ns (1) t sldv chip select low to data valid 4t C 32 ns (1) t chdv clkout high to input data valid 2t C 25 ns t rhdz end of rd# to input data float t C 5 ns t rxdx data hold after rd# inactive 0 ns t avyv ad15:0 valid to ready setup 2t C 38 ns (2) t clyx ready hold after clkout low 0 2t C 36 ns (3) t ylyh non-ready time no upper limit ns notes: 1. if wait states are used, add 2t n , where n = number of wait states. 2. when forcing wait states using the buscon register, add 2t n. 3. exceeding the maximum specification causes additional wait states. table 12. ac characteristics the 8XC196NU will meet, multiplexed bus mode (continued) symbol parameter min max units notes: 1. 25 mhz is the maximum input frequency when using an external crystal oscillator; however, 50 mhz can be applied with an external clock source. 2. when the phase-locked loop (pll) circuitry is enabled, the minimum input frequency on xtal1 is 8 mhz. the pll cannot be run at frequencies lower than 16 mhz. 3. if wait states are used, add 2t n , where n = number of wait states. 4. assuming back-to-back bus cycles. 5. 8-bit bus only.
preliminary 27 8XC196NU commercial chmos 16-bit microcontroller 6.2.3.1 system bus timings, multiplexed bus figure 7. system bus timings, multiplexed bus mode clkout ale rd# a4389-01 ad15:0 (read) wr# ad15:0 (write) a19:16 t lhlh valid address out extended address out t t cllh t clcl t chdv t rlcl t chcl t llch t llrl t rhlh t rlrh t rldv t rhdz data in t rlaz t llax address out t avdv t avll t chwh t whlh t llwl t wlwh t whqx data out address out t wlwh t qvwh t whbx , t rhbx high address out t whsh , t rhsh cs x # t whax , t rhax t lhll ? bhe#, inst ? 80c196nu a-1 step ?? 80c196nu b step and 83c196nu ad15:8 valid ?? bhe#, inst valid
28 preliminary 8XC196NU commercial chmos 16-bit microcontroller 6.2.3.2 ready timing, multiplexed bus figure 8. ready timing, multiplexed bus mode clkout ready ale a4388-01 t clyx (min) t lhlh + 2t t avdv + 2t rd# ad15:0 (read) ad15:0 (write) ?? bhe#, inst valid valid a19:0 cs x # t rlrh + 2t t avyv extended address out t clyx (max) data in t rldv + 2t t wlwh + 2t t qvwh + 2t wr# data out valid ? bhe#, inst ? 80c196nu a-1 step ?? 80c196nu b step and 83c196nu
preliminary 29 8XC196NU commercial chmos 16-bit microcontroller 6.2.4 ac characteristics demultiplexed bus mode test conditions: capacitive load on all pins = 50 pf, rise and fall times = 3 ns. table 14. ac characteristics the 8XC196NU will meet, demultiplexed bus mode symbol parameter min max units f xtal 1 frequency on xtal1, pll in 1x mode 16 50 (1) mhz frequency on xtal1, pll in 2x mode 8 (2) 25 mhz frequency on xtal1, pll in 4x mode 8 (2) 12.5 mhz f operating frequency, f = f xtal 1 ; pll in 1x mode 16 50 mhz operating frequency, f = 2f xtal 1 ; pll in 2x mode operating frequency, f = 4f xtal 1 ; pll in 4x mode t period, t = 1/f 20 62.5 ns t avwl address valid to wr# falling edge t C 8 ns(3) t avrl address valid to rd# falling edge t C 8 ns(3) t rhrl read high to next read low t C 5 ns(3) t xhch xtal1 high to clkout high or low 3 50 ns t clcl clkout cycle time 2t ns t chcl clkout high period t C 10 t + 15 ns t cllh clkout falling edge to ale rising edge C 10 10 ns t llch ale falling edge to clkout rising edge C 15 15 ns t lhlh ale cycle time 4t ns (3,4,5) t lhll ale high period t C 10 t + 10 ns t rlcl rd# low to clkout falling edge C 5 11 ns t rlrh rd# low period 3t C 18 ns (4) t rhlh rd# rising edge to ale rising edge t C 4 t + 15 ns ( 3 ) t wlcl wr# low to clkout falling edge C 8 5 ns t qvwh data stable to wr# rising edge 3t C 25 ns (4) t chwh clkout high to wr# rising edge C 11 10 ns t wlwh wr# low period 3t C 18 ns (4) t whqx data hold after wr# rising edge t t + 20 ns notes: 1. 25 mhz is the maximum input frequency when using an external crystal oscillator; however, 50 mhz can be applied with an external clock source. 2. when the phase-locked loop (pll) circuitry is enabled, the minimum input frequency on xtal1 is 8 mhz. the pll cannot be run at frequencies lower than 16 mhz. 3. for deferred bus cycle, add 2t (1 state) if cs x # changes or if the write cycle follows a read cycle. 4. if wait states are used, add 2t n , where n = number of wait states. 5. assuming back-to-back bus cycles.
30 preliminary 8XC196NU commercial chmos 16-bit microcontroller t whlh wr# rising edge to ale rising edge t C 5 t + 10 ns (3) t whbx bhe#, inst hold after wr# rising edge a-step b-step t C 5 0 ns t whax a19:0, cs x # hold after wr# rising edge 0 ns t rhbx bhe#, inst hold after rd# rising edge a-step b-step t C 5 0 ns t rhax a19:0, cs x # hold after rd# rising edge 0 ns table 15. ac characteristics the external memory system must meet, demultiplexed bus mode symbol parameter min max units t avdv a19:0 valid to input data valid 4t C 25 ns (1,2) t rldv rd# active to input data valid 3t C 35 ns (1) t sldv chip select low to data valid 4t C 25 ns (1,2) t chdv clkout high to input data valid 2t C 25 ns t rhdz end of rd# to input data float t ns t rxdx data hold after rd# inactive 0 ns t avyv a19:0 valid to ready setup 3t C 45 ns (3) t clyx ready hold after clkout low 0 2t C 26 ns (4) t ylyh non ready time no upper limit ns notes: 1. if wait states are used, add 2t n , where n = number of wait states. 2. for deferred bus cycle, add 2t (1 state) if cs x # changes or if the write cycle follows a read cycle. 3. when forcing wait states using the buscon register, add 2t n. 4. exceeding the maximum specification causes additional wait states. table 14. ac characteristics the 8XC196NU will meet, demultiplexed bus mode (continued) symbol parameter min max units notes: 1. 25 mhz is the maximum input frequency when using an external crystal oscillator; however, 50 mhz can be applied with an external clock source. 2. when the phase-locked loop (pll) circuitry is enabled, the minimum input frequency on xtal1 is 8 mhz. the pll cannot be run at frequencies lower than 16 mhz. 3. for deferred bus cycle, add 2t (1 state) if cs x # changes or if the write cycle follows a read cycle. 4. if wait states are used, add 2t n , where n = number of wait states. 5. assuming back-to-back bus cycles.
preliminary 31 8XC196NU commercial chmos 16-bit microcontroller 6.2.4.1 system bus timings, demultiplexed bus figure 9. system bus timings, demultiplexed bus mode clkout ale rd# a4390-01 ad15:0 (read) wr# ad15:0 (write) ? bhe#, inst ?? bhe#, inst a19:0 valid valid address out t chcl t clcl t llch t chwh t lhlh t whlh t rhrl t rhdz data in t rlrh t avdv t whqx t whax t wlcl data out t wlwh t qvwh t whbx ,t rhbx cs x # t lhll t cllh t t rhlh t avrl t rhax t sldv t chdv t rldv t avwl ? 80c196nu a-1 step ?? 80c196nu b step and 83c196nu valid
32 preliminary 8XC196NU commercial chmos 16-bit microcontroller 6.2.4.2 ready timing, demultiplexed bus figure 10. ready timing, demultiplexed bus mode clkout ready ale a4391-01 t clyx (min) t lhlh + 2t t avdv + 2t rd# ad15:0 (read) ad15:0 (write) a19:16 cs x # t rlrh + 2t t avyv valid data out extended address out address out t clyx (max) data in address out t rldv + 2t t wlwh + 2t t qvwh + 2t wr# ? bhe#, inst ?? bhe#, inst ? 80c196nu a-1 step ?? 80c196nu b step and 83c196nu valid valid
preliminary 33 8XC196NU commercial chmos 16-bit microcontroller 6.2.4.3 8XC196NU deferred bus timing mode the deferred bus cycle mode (enabled by setting ccb1.5) is designed to reduce bus contention when using the 8XC196NU in demultiplexed mode with slow memories. when the deferred mode is enabled, a delay will occur (equal to 2t) in the first bus cycle following a chip-select ch ange or the first write cycle following a read cycle. this mode will work in parallel with wait states. refer to figure 11 to determine which control signals are affected. cycle 1 is a normal 4t read cycle. cycle 2 is a write cycle that follows a read cycle, so a 2t delay is inserted. notice that the chip-select change at the beginning of cycle 2 did not cause a double delay (4t). the chip-select change in cycle 3, a read cycle, causes a 2t delay. figure 11. deferred bus mode timing diagram clkout ale rd# a5097-01 t whlh + 2t t rhlh + 2t t avrl + 2t t avwl + 2t ad15:0 (read) wr# ad15:0 (write) ? bhe#, inst ?? bhe#, inst a19:0 cs x # t avdv , t sldv + 2t t lhlh + 2t valid valid data out valid valid data out data out address out ? 80c196nu a-1 step ?? 80c196nu b step and 83c196nu
34 preliminary 8XC196NU commercial chmos 16-bit microcontroller 6.2.5 hold#, hlda# timings figure 12. hold#, hlda# timing diagram table 16. hold#, hlda# timings symbol parameter min max units t hvch hold# setup time (to guarantee recognition at next clock) 65 ns t clhal clkout low to hlda# low C15 15 ns t clbrl clkout low to breq# low C15 15 ns t halaz hlda# low to address float 33 ns t halbz hlda# low to bhe#, inst, rd#, wr# weakly driven 25 ns t clhah clkout low to hlda# high C25 15 ns t clbrh clkout low to breq# high C25 25 ns t hahax hlda# high to address no longer float C20 ns t hahbv hlda# high to bhe#, inst, rd#, wr# valid C20 ns a2460-03 clkout hold# hlda# breq# a19:0, ad15:0 cs x #, bhe#, inst, rd#, wr# wrl#, wrh# ale t cllh t clhah t clbrh t hahax t hahbv t halbz t halaz t clbrl t clhal t hvch t hvch hold latency start of strongly driven ale weakly held inactive
preliminary 35 8XC196NU commercial chmos 16-bit microcontroller 6.2.6 ac characteristics serial port, synchronous mode 0 figure 13. serial port waveform synchronous mode 0 table 17. serial port timing synchronous mode 0 symbol parameter min max units t xlxl serial port clock period sp_baud 3 x 002h sp_baud = x 001h (note 1) 6t 4t ns ns t xlxh serial port clock falling edge to rising edge sp_baud 3 x 002h sp_baud = x 001h (note 1) 4t C 27 2t C 27 4t + 27 2t + 27 ns ns t qvxh output data setup to clock high 4t C 30 ns t xhqx output data hold after clock high 2t C 30 ns t xhqv next output data valid after clock high 2t + 30 ns t dvxh input data setup to clock high 2t + 30 ns t xhdx input data hold after clock high 0 ns t xhqz last clock high to output float t + 30 ns note: 1. the minimum baud-rate (sp_baud) register value for receive is x 002h and the minimum baud-rate (sp_baud) register value for transmit is x 001h. valid valid valid valid valid valid valid valid rxd (in) (out) txd 01 2 3 4 5 6 7 t qvxh t xlxl t dvxh t xhqv t xhqz t xhdx t xhqx t xlxh a2080-02 rxd
36 preliminary 8XC196NU commercial chmos 16-bit microcontroller 6.2.7 external clock drive figure 14. external clock drive waveforms figure 15. ac testing output waveforms during 5.0 volt testing table 18. external clock drive symbol parameter min max units f xtal 1 external input frequency (1/ t xlxl ), pll disabled 16 50 ? mhz external input frequency (1/ t xlxl ), pll in 2x mode 8 25 mhz external input frequency (1/ t xlxl ), pll in 4x mode 8 12.5 mhz t xtal 1 oscillator period (t xlxl ), pll disabled 20 62.5 ns oscillator period (t xlxl ), pll in 2x mode 40 125 ns oscillator period (t xlxl ), pll in 4x mode 80 125 ns t xhxx high time 0.35t xtal 1 0.65t xtal 1 ns t xlxx low time 0.35t xtal 1 0.65t xtal 1 ns t xlxh rise time 10 ns t xhxl fall time 10 ns ? assumes an external clock; the maximum input frequency for an external crystal oscillator is 25 mhz. a2119-02 t xhxx t xlxx t xhxl t xlxl 0.3 v cc C 0.5 v 0.7 v cc + 0.5 v t xlxh 0.7 v cc + 0.5 v 0.3 v cc C 0.5 v test points 2.0 v 0.8 v ac testing inputs are driven at 3.5 v for a logic "1" and 0.45 v for a logic "0". timing measurements are made at 2.0 v for a logic "1" and 0.8 v for a logic "0". 3.5 v 0.45 v a2120-02 2.0 v 0.8 v
preliminary 37 8XC196NU commercial chmos 16-bit microcontroller figure 16. float waveforms during 5.0 volt testing v load + 0.15 v v load C 0.15 v timing reference points v load v oh C 0.15 v v ol + 0.15 v for timing purposes, a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loading v oh /v ol level occurs with i ol /i oh 15 ma. a2121-01
38 preliminary 8XC196NU commercial chmos 16-bit microcontroller 7.0 thermal characteristics all thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. values will change depending on operating conditions and the application. the intel packaging handbook (order number 240800) describes intels thermal impedance test methodology. the components quality and reliability handbook (order number 210997) provides quality and reliability information. 8.0 8XC196NU errata the 8XC196NU may contain design defects or errors known as errata. characterized errata that may cause the 8XC196NUs behavior to deviate from published specifications are documented in the 8XC196NU specification update (272864-001). specification updates can be obtained from your local intel sales office or from the world wide web ( www.intel.com ). 9.0 datasheet revision history this datasheet is valid for devices with a b or c designation at the end of the topside tracking number. datasheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. this is the -004 version of the datasheet. the following changes were made in this version: 1. all references to advance information have been changed to preliminary. 2. table note added to tables 4 and 6. 3. table 15, removed note (2) attachment from t rhdz . 4. table 15, specification change made to the fol- lowing timings: t avdv , t sldv , t clyx . this is the -003 version of the datasheet. the following changes were made in this version: 1. a heading was added for section 1.0, product overview, and the remaining sections were renumbered. 2. list of features, the 8XC196NU has four options (0C3) for programmable wait states for each chip select, not sixteen (0C15) as previ- ously stated. 3. the rom sqfp (sb83c196nu) pinout and pin assignment tables have been deleted. 4. figure 5, package designator in diagram changed to s from sb to correctly indicate the qfp package type. 5. table 8, ea# signal description added. 6. table 8, signal descriptions for breq#, hlda#, hold#, pllen2:1, and reset# have been modified. 7. table 9, redesigned and footnotes reordered. 8. table 10, v ih 2 specification added with foot- note. 9. figure 6, corrected to state pllen2:1=01 (not pllen2:1=10). 10. tables 12 and 14, b-step timing added for t whbx min and t rhbx min. 11. table 12, deleted notes 4 and 5, added note 2, and reordered remaining notes. 12. table 13, deleted notes 1, 3, and 6 and reor- dered remaining notes. 13. table 14, deleted notes 4, 5, and 6, added note 2, and reordered remaining notes. 14. table 15, deleted notes 1, 3, and 6 and reor- dered remaining notes. 15. tables 13 and 15, the minimum timing for t rxdx improved from 2 ns to 0 ns. 16. figures 7C11, updated to reflect both a- and b- step timings on the bhe#, inst signal. 17. section 5.4.3, the second sentence of the first paragraph, the word and replaced by or. 18. table 19, thermal characteristics specifications have been changed and expanded. 19. the errata list was replaced with a reference to the specification update document. the following changes were made in the -002 version of the datasheet: 1. the input frequency on xtal1, formerly called f osc , is now called f xtal 1 . the internal operat- ing frequency and operating period are denoted by (f) and (t), respectively. 2. 25 mhz is the maximum input frequency when using an external crystal oscillator; however, 50 mhz can be applied with an external clock source. table 19. thermal characteristics package type q ja q jc 100-pin qfp 80c196nu 55 c/w 11 c/w 100-pin sqfp 80c196nu 66 c/w 16.5 c/w 100-pin qfp 83c196nu 55 c/w 11 c/w
preliminary 39 8XC196NU commercial chmos 16-bit microcontroller 3. the minimum frequency input with pll in 4x mode has changed from 4 mhz to 8mhz. 4. the ac characteristics tables have been divided into the following: the timing specifica- tions met by the device, and the timing specifi- cations that must be met by the external memory system. 5. electrical characteristics notes #2 and #3 added to section 3.0. 6. maximum i ol and i oh specifications added to the dc characteristics tables. 7. ac timings t avwl and t sldv added to the ac characteristicsCmultiplexed bus mode tables. 8. figure 7 added, and figures 8C12 have been revised. 9. thermal characteristics for the 100-pin sqfp package have been added in section 1.0. 10. specifications for the 83c196nu have been added. 11. several ac timing specifications have changed.

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